library ieee;
use ieee.std_logic_1164.all;
entity oneMHZ is
port( clkin:in std_logic; --时钟信号输入
clkout:out std_logic); --时钟信号输出
end oneMHZ;
architecture aroneMHZ of oneMHZ is
signal data:integer range 0 to 10;
signal Q:std_logic;
begin
process(clkin)
begin
if rising_edge(clkin) then
if(data=0) then --此句为你想要的分频比,data=0,1,2,3,4.......9的分频比为1,2,3,,,10
data<=0;
Q<=not Q;
else
data<=data+1;
end if;
end if;
clkout<=Q;
end process;
end oneMHZ;
我试了楼上的vhdl,结果是这样的,
data=0, 二分频
data=1,四分频
data=2,六分频
data=3,八分频
data=4,十分频
data=5,十二分频
~~~